Building an enhanced intelligent 4-20mA transmitter based on MAXQ microcontroller

A typical 4-20mA current loop circuit includes four parts: sensor / transmitter, voltage-current converter, loop power supply, and receiver / monitor. In the application of loop power supply, the sensor drives the voltage-current converter, and the other three parts are connected in series to form a closed loop (Figure 1).

Figure 1. Block diagram of 4-20mA loop power supply circuit

The smart transmitter can calibrate the gain and offset, linearize the sensor analog signal (such as RTD sensor and thermocouple), process the signal with a mathematical algorithm residing inside the µC, and then convert the digital signal back Analog signal, the result is transmitted along the loop in the form of standard current.

The latest third-generation 4-20mA transmitter (Figure 2) is considered an "enhanced smart" transmitter. They increase the digital communication function of sharing twisted pair with 4-20mA signal. The provided communication channel can transmit control and diagnostic signals while transmitting sensor data.

Figure 2. 4-20mA enhanced smart transmitter block diagram

The communication standard used by the smart transmitter is the Hart protocol, which is based on the Bell 202 telephone communication standard and uses frequency shift keying (FSK). The digital signals 1 and 0 are represented by frequencies of 1200 Hz and 2200 Hz, respectively. Sine waves of these frequencies are superimposed on the DC analog signal of the sensor, providing both analog and digital communication (Figure 3).

Figure 3. Simultaneous communication of analog and digital signals

Because the average value of the FSK signal is always zero, the 4-20mA analog signal is not affected in this process. The digital state can be switched two to three times per second without interfering with the analog signal. The minimum allowable loop impedance is 23 .

Figure 4. Block diagram of MAXQ µC architecture

The software-selectable clock divider operation allows flexible selection of 1, 2, 4, or 8 oscillator cycles as a system clock cycle. This function is implemented through software, so µC can enter a low-power state without adding additional hardware costs.

It also provides three other low-power modes for applications that are extremely sensitive to power consumption:

In PMM1 mode, one system clock cycle is equal to 256 oscillator cycles, and µC works at reduced speed, which greatly reduces power consumption. In PMM2 mode, the device uses a 32kHz oscillator as the clock source and operates at a lower speed. When an enabled interrupt source interrupts, the optional clock return function allows the device to quickly exit power management mode and return to a faster internal clock frequency. These enabled interrupt sources can be external interrupts, UART and SPI modules. All these features bring MAXQ µC's processing power to 3MIPS / mA, and its performance far exceeds the closest other processors (Figure 5).

Figure 5. MIPS / mA performance comparison between MAXQ and other competing products.

y [n] = bix [ni] + aiy [ni]

In the formula, bi and ai respectively characterize the feedforward and feedback response characteristics of the system. According to the different values ​​of ai and bi, digital filters can be divided into finite-length impulse response type (FIR) or infinite-length impulse response type (IIR). When the system does not include feedback (all ai = 0), the filter is of FIR type:

y [n] = bix [ni]

However, if both ai and bi are not zero, the filter is of type IIR.

It can be seen from the above FIR filter equation that the main mathematical operation is to multiply each input sample by a constant, and then accumulate and add n multiplications. The following C program can illustrate the operation:

x [0] move DP [1], #b; DP [1]-> b [0] move LC [0], #loop_cnt; LC [0]-> number of samples move MCNT, #INIT_MAC; IniTIalize MAC unit MAC_LOOP: move DP [0], DP [0]; AcTIvate DP [0] move MA, @DP [0] ++; Get sample into MAC move DP [1], DP [1]; AcTIvate DP [1] move MB, @DP [1] ++; Get coeff into MAC and mulTIply djnz LC [0], MAC_LOOP. (See the appendix for the details of the data memory access for MAXQ architecture).

Note: In the MAXQ MAC, when the second operand is loaded, the requested operation is automatically performed, and the operation result is stored in the MC register. Also note that before overflow, the MC register width (40 bits) can accumulate a large number of 32-bit multiplication results. This function is an improvement to the traditional method, which has to verify whether it overflows after each basic operation.

MAXQ2000 µC's unique performance low-power, 16-bit RISC microcontroller MAXQ2000 is the first member of the Maxim MAXQ family. It has a liquid crystal display (LCD) interface and can drive up to 100 (-RBX) or 132 (-RAX) segments. MAXQ2000 is extremely suitable for blood glucose monitoring applications, and is suitable for any application that requires high performance and low power consumption. The maximum operating frequency is 14MHz (VDD> 1.8V) or 20MHz (VDD> 2.25V).

The MAXQ2000 contains 32k words of flash memory (suitable for prototyping and small batch production), 1k words of RAM, three 16-bit timers, and one or two universal synchronous / asynchronous transceivers (UART). For flexibility, the microcontroller core power supply (1.8V) is independent of the I / O subsystem power supply. The ultra-low-power sleep mode makes the MAXQ2000 ideal for portable and battery-powered equipment.

The powerful MAXQ2000 µC of the MAXQ2000 evaluation board can be evaluated using its evaluation board (EV), which provides a complete MAXQ2000 hardware development environment (Figure 6).

Figure 6. Block diagram of the MAXQ2000 evaluation board

The MAXQ2000 evaluation board has the following characteristics:

Onboard MAXQ2000 core power supply and VDDIO power supply. Adjustable power supply (1.8V to 3.6V) can be used as VDDIO or VLCD power supply. Correspond to the plug pins of all signals and power supply of MAXQ2000. Independent LCD daughter board connector. The LCD daughter board is equipped with a 3V, 3.5-bit static LCD display. RS-232 level driver connected to serial UART (port 0), including flow control line. External interrupt button and microcontroller system reset button. The MAX1407 multi-function ADC / DAC chip is connected to the MAXQ2000 SPI bus interface. 1-Wire interface and 1-Wire EEPROM chip. Bar LED display indicates the level status of port pins P0.7 to P0.0. JTAG interface, used for application download and debugging in the system. Therefore, the MAXQ2000 evaluation board has all the functions needed to build an intelligent 4-20mA transmitter: low power µC with a true multiply-accumulate unit (for filtering and frequency encoding / decoding); ADC that converts the sensor signal; generation Analog output signal DAC (Figure 7). Coupled with a low-power Codec, such as MAX1102, you can implement a HART modem.

Figure 7. 4-20mA transmitter based on MAXQ2000 µC

Implementation of HART Modem If the system contains 1200Hz and 2200Hz (representing 1 and 0) frequency encoders, at the same time to detect these frequencies, you can use MAC to achieve these functions required by HART modem.

To generate the desired sinusoidal waveform, a recursive digital resonator can be implemented using the form of a two-pole filter described by the following difference equation:

Xn = k * Xn-1-Xn-2,

In the formula, the constant k is equal to 2 cos (2 * Frequency / Sampling rate). Two values ​​of k can be calculated in advance and stored in ROM. For example, to generate a frequency of 1200 Hz with a sampling rate of 8 kHz, the value is k = 2 cos (2 * 1200/8000).

The initial stimulus that can start the oscillator to oscillate must be calculated. If Xn-1 and Xn-2 are both 0, each subsequent Xn will also be 0. To start the oscillator, set Xn-1 to 0 and Xn-2 to use the following settings:

Xn-2 = -A * sin [2 (Frequency / Sampling Rate))

In this example, assuming a unit amplitude sine wave, the formula is simplified to Xn-2 = -1sin [(2 (1200/8000)]. To further simplify coding, first, initialize two intermediate variables (X1, X2). X1 is initialized to 0, and X2 is the initial excitation value (the calculation result above) to start the oscillator. In this way, to generate a sine wave sample, you can perform the following operations:

X0 = kX1-X2 X2 = X1 X1 = X0 Each new sine value requires a multiplication operation and a subtraction operation. Using MAXQ µC's single-cycle hardware MAC, the following operations can be used to generate a sine wave: move DP [0], # X1; DP [0]-> X1 move MCNT, #INIT_MAC; Initialize MAC unit move MA, #k; MA = k move MB, @DP [0] ++; MB = X1, MC = k * X1, point to X2 move MA, # -1; MA = -1 move MB, @DP [0]-; MB = X2 , MC = k * X1-X2, point to X1 nop; wait for result move @-DP [0], MC; Store result at X0. Because we only need to detect two frequencies, the improved Goertzel algorithm is used, which This algorithm can be implemented with a simple second-order filter (Figure 8).

Figure 8. Using a simple second-order filter to implement the Goertzel algorithm

To use the Goertzel algorithm to detect a specific frequency, you must first calculate the constant using the following formula when compiling:

k = tone frequency / sampling rate a1 = 2cos (2 k) Subsequently, the intermediate variables D0, D1 and D2 are initialized to 0, and the following calculations are performed for each received sample X: D0 = X + a1 * D1-D2 D2 = D1 D1 = D0 to get enough samples In the future (usually 205 samples when using 8kHz sampling rate), use the latest calculated D1 and D2 values ​​to perform the following calculations: P = D12 + D22-a1 * D1 * D2. At this time, P includes the input signal test The square of the frequency.

To decode two frequencies, we use two filters to process each sample. Each filter has its own k value and its own set of intermediate variables, each variable is 16 bits long, so the entire algorithm requires 48 bytes of intermediate memory space.

Appendix. Access to the data memory of the MAXQ series can be accessed through the data pointer registers DP [0] and DP [1], or through the frame pointer BP (offset). When one of the registers is set to a location in the data memory, you can use the mnemonic @DP [0], @DP [1], or @BP [OFFS] as the source or target to read and write access to the memory location. move DP [0], # 0000h; set pointer to location 0000h move A [0], @DP [0]; read from data memory move @DP [0], # 55h; write to data memory after a read operation, Either of the two data pointers can be automatically incremented or decremented after the operation is completed. In addition, any data pointer can be incremented or decremented before the write operation. Use the following syntax rules: move A [0], @DP [0] ++; increment DP [0] after read move @ ++ DP [0], A [1]; increment DP [0] before write move A [ 5], @DP [1]-; decrement DP [1] after read move @-DP [1], # 00h; decrement DP [1] before write because three pointers share a data memory read / write port, Therefore, the user must consciously activate the pointer before using a specific pointer to read the data memory. As shown below, this can be achieved directly by using the data pointer selection bits (SDPS1: 0; DPC.1: 0), or indirectly by writing the DP [n], BP, or OFFS registers.

When using the data pointer for indirect memory write operations, the SDPS bit is set, which then activates the write pointer as the active source pointer.

move DPC, # 2; (explicit) selection of FP as the pointer move DP [1], DP [1]; (implicit) selection of DP [1]; set SDPS1: 0 = 01b move OFFS, src; (implicit) selection of FP; set SDPS1 = 1 move @DP [0], src; (implicit) selection of DP [0]; set SDPS1: 0 = 00b Once the pointer is selected, the pointer remains valid until the following events occur: Source The data pointer selection bit is changed by the above-mentioned direct or indirect method (that is, another data pointer is selected), or the memory addressed by the active source data pointer is enabled for code extraction, which is achieved using the instruction pointer, or using a current A data pointer other than the active source pointer performs a memory write operation. move DP [1], DP [1]; select DP [1] as the active pointer move dst, @DP [1]; read from pointer move @DP [1], src; write using a data pointer; DP [0 ] is needed move DP [0], DP [0]; select DP [0] as the active pointer To simplify the increment / decrement of the data pointer without affecting the register data, register 7 in system module 6 is designated as Virtual NUL target, used as a bit bucket. The data pointer increment / decrement operation can be completed by the following operations without changing the contents of any other registers: move NUL, @DP [0] ++; increment DP [0] move NUL, @DP [0]-; decrement DP [0]