Core Guide: The design of signal generation and measurement of power supply using discrete components or CPLDs and FPGAs will increase the complexity of hardware design and extend the development cycle. In order to simplify the hardware design of power signal generation and measurement and shorten the development cycle, this paper proposes a DSP-based embedded operation platform, which adopts the design scheme of DDS (direct digital frequency synthesizer) and multiplier vector measurement technology. This solution utilizes the high-speed computing power of DSP to realize the hardware logic functions of discrete components or CPLDs and FPGAs through real-time calculation. The experimental results show that the scheme is feasible.

0 Preface

The signal measurement and control part of the power supply consists of DDS signal generation and signal measurement. The use of DDS in power supply design has long existed. In the early DDS design, the hardware consisted of a variety of discrete logic components such as counters and flip-flops. After the emergence of the programmable logic devices CPLD and FPGA, the hardware structure of the DDS was simplified. The signal measurement of the power supply is divided into frequency, amplitude and phase measurements. The frequency is measured by pulse filling method; the amplitude measurement is developed by the original RMS conversion with large delay and the real-time sampling calculation with the increase of the sampling speed and processor speed of the A/D converter; Based on the amplitude measurement, the original interphase pulse filling method is developed to multiplier vector measurement.

The high-speed processing capability of the DSP makes it possible to implement the functions of the analog digital hybrid multiplier in the CPLD or FPGA and measurement circuit in the DDS, thus making the hardware design of the signal generation and measurement of the power supply simpler.

1 design plan

The scheme design is shown in Figure 1. The DSP quickly and continuously reads the waveform data in the extended program memory at equal time intervals, and feeds the parallel high-speed D/A. The parallel high-speed D/A can output the preset signal waveform.

The adjustment of the output signal amplitude is not as frequent as the waveform data read operation, and the length and accuracy of the operation completion time are not as high as the waveform data read, so serial multi-channel D/A is selected. This can reduce costs and simplify some hardware designs. Based on the N waveform read time interval, the DSP continuously samples the signal processed signal through parallel high-speed A/D, and calculates the effective value and phase of the measured signal.

2 DSP implementation of DDS

2. DDS principle

DDS is a frequency synthesis technique that directly synthesizes a desired waveform using the phase accumulation principle. A typical DDS model consists of a W-bit phase accumulator, a phase shift adder, a waveform memory ROM look-up table (LUT), and a D/A converter ( DAC) and low pass filter (LPF). The phase accumulator is composed of a W-bit adder and a W-bit accumulation register.

When the DDS is operating, for each clock pulse p, the adder adds the phase step value Δθ to the accumulated phase data output from the accumulation register, and sends the added result to the data input terminal of the accumulation register.

The accumulation register feeds back the new phase data generated by the adder after the last clock pulse to the input of the adder, so that the adder continues to add the frequency control word under the action of the next clock pulse. The data output by the phase accumulator is used as a table lookup address, and the corresponding waveform sample value (binary code) is extracted from the waveform memory (ROM) and sent to the D/A converter C. In the data output range of the phase accumulator 0 ~ 2W - 1, and the address of a complete periodic waveform in the waveform memory, according to a specific functional relationship, each time the phase accumulator overflows, the DDS outputs accordingly. A cycle of waveforms. Therefore, the overflow frequency of the phase accumulator is the signal frequency of the DDS output. From this, the signal frequency formula of the DDS output can be derived:

It can be seen from equation (1) that when the phase accumulator width W is constant and the phase step value Δθ is 1, the minimum output frequency of the DDS, that is, the frequency resolution fr of the DDS can be obtained. Therefore, it is only necessary to adjust the phase step value Δθ so that the frequency of the DDS can be output as an integer multiple of fr.

2. 2 DDS working mode selection

According to the formula, the output frequency of the DDS depends on Δθ and fclk on the premise that the phase accumulator width W is constant.

When Δθ is the phase resolution of DDS, each period of DDS output signal is composed of fixed points. At this time, fout is proportional to fclk, DDS is frequency modulation mode; when fclk is constant, DDS output signal is in unit time It consists of fixed points, where fout is proportional to Δθ and DDS is phasing mode.

In the FM mode, the key point is to use the phase-locked loop technology to multiply the preset output frequency [3 - 4]. Compared with the phase modulation mode, the frequency modulation mode not only needs more design of the phase-locked loop and the corresponding frequency multiplying logic circuit, and when the frequency is adjusted, the signal will lose lock for a short time, causing the output signal to oscillate. Therefore, the phase modulation mode is the best choice for DDS in this design.

2. 3 DSP realizes the advantages of DDS

Whether using discrete logic devices or CPLD or FPGA design DDS, the purpose is to achieve the high-speed implementation of the phase accumulator accumulation, output, waveform data lookup table and other operations through the hardware circuit. The only difference is that the CPD or FPGA design DDS can be used to simplify the hardware circuit design by programming the logic circuits implemented by many discrete devices through a programming language such as VHDL. The use of DSP design DDS, you can fully use its high-speed computing capabilities, through the software programming to complete the accumulator accumulator, output, waveform data table and other operations. Therefore, using DSP to design DDS is more flexible and efficient than using CPLD or FPGA.