Implementation of Audio Acquisition Card Based on FPGA and DSP

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Abstract : This paper introduces a design and implementation scheme of multi-channel audio capture card based on FPGA and DSP. The card can work at various sampling rates and can use different audio algorithms in DSP to meet different occasions. The PC104 interface uploads the processed data to the host. The acquisition card has been used in the ship navigation data recorder VDR.
Key words: FPGA; DSP; PC104; multi-sampling rate; audio data compression; navigation data recorder VDR

0 Preface

A multi-channel digital audio system must consider two issues: the quality of the sound collected and the problem of the final digitized audio storage. According to Nyquist's theorem, if the recovered audio signal is to be recovered completely without distortion, the sampling rate must be at least twice the bandwidth of the audio signal to be acquired. Since most audio CODECs now use the Delta-Sigma Modulator, the sound quality is generally satisfactory when the sampling rate is guaranteed to be appropriate. In the ship navigation recorder, the bandwidth of the audio is 150hz-6000hz, so we can use the sampling rate of 16khz and the number of quantized bits of 16 bits.

According to this sampling rate, the single-channel audio code rate is 256 kbps, and the data volume of the 24-hour audio is as high as 2.76 GB. In order to reduce the storage space of the final memory, the original audio data needs to be compressed. In general, lossy compression is much higher than lossless compression, but at the same time it causes a drop in sound quality. The system should be designed with the right balance.

The multi-channel audio capture card based on FPGA and DSP designed in this paper uses Altera's Cyclone series FPGA to simplify logic control and improve hardware speed. TI's TMS320VC 5416 is used to implement audio compression algorithm, which reduces the audio performance index. The final amount of audio data meets the design requirements of the system.

1 system hardware structure

1.1 main chip selection

(1) Audio CODEC chip PCM3008

The PCM3008 from Texas Instruments was used in the selection of the audio CODEC chip. This audio CODEC chip uses a 16-bit delta-sigma ADC and DAC. The stereo ADC has a single-ended voltage input and a built-in anti-aliasing filter. Excellent performance is also reflected in its ADC's total harmonic distortion plus noise as low as -84dB, signal-to-noise ratio as high as 88dB, dynamic range to 88dB, and its built-in 1/64× Decimation digital filter allows the signal to fluctuate within the passband only With ±0.05dB, the stopband attenuation can be -65dB. Low voltage operation, low power consumption. Its sampling rate is 8khz-48khz optional. The data transmission is a synchronous serial port mode, which is convenient to operate.

(2) FPGA chip EP1C6Q240

The FPGA uses the EP1C6Q240 of Altera's Cyclone series to implement interface control of each device. The Cyclone family of FPGAs is Altera's low-cost, high-performance application with a high price/performance ratio. EP1C6Q240's maximum available IO number is 185; on-chip 92Kbit RAM can be configured as single dual-port RAM, ROM, FIFO and other storage modules; two high-precision phase-locked loops, which conveniently provide the required clocks for each module in the chip. 5980 LEs (Logical Units) provide rich logic resources for the implementation of interface circuits. Altera's Quartus II integrated development environment is easy to use, contains a large number of IP cores, and its built-in Signal Tap II logic analyzer provides users with a lot of convenience.

(3) DSP chip TMS320VC5416

The DSP chip uses TI's TMS320VC5416. The TMS320VC5416 is a high-performance, low-power fixed-point DSP from TI's 5000 series based on the C54x DSP core. The TMS320VC5416 is a 16-bit fixed-point high-performance digital signal processor with the following features: Up to 160MIPS; 3 16-bit data memory bus and 1 program memory bus; 1 40-bit barrel shifter and 2 40-bit accumulator; 1 17×17 multiplier and 1 40-bit dedicated adder; maximum 8M × 16-bit extended addressing space, built-in 128 k × 16-bit RAM and 16 k × 16-bit ROM; Multi-channel buffered serial port (McBSP); its rich peripherals and powerful computing capabilities make the TMS320VC5416 capable of real-time multi-channel audio processing. In the implementation of compression, the use of the general-purpose DSP chip TMS320VC5416 compared with the use of a dedicated hardware compression chip, not only can save costs, but also can easily achieve system upgrades and flexible configuration.

figure 1

1.2 System Design Ideas

The hardware structure design is shown in Figure 1. The multi-channel audio signal first passes through the conditioning part, enters the audio CODEC PCM3008, and sends the audio data into the RAM of the DSP through the three signal lines BCK, LRCK, and DOUT. The DSP will arrange one frame of audio data in one order according to a certain order. In the cache, the audio compression algorithm is sequentially called for each audio data, and the data is sent to the SRAM through the SRAM controller in the FPGA before the next frame of audio data arrives in the buffer area, and the PC 104 host is notified of the acquisition process. The PC104 host reads the data in the cache SRAM through the PC104 interface module in the FPGA.

2 FPGA functional module design

The design of the FPGA uses a modular design philosophy. The main modules are divided by function as shown in Figure 2. The SRAM controller uses a ping-pong mechanism, one in the state of reading data, and the other in the state of writing data, switching every 15 seconds under the control of the PC104 host. This operation mode has a simple and reliable timing design, and is easy to operate audio data continuously. After receiving the switching command issued by the PC104 host, when two SRAMs are idle, the two SRAM read and write switches are completed. At the same time of switching, the address of the SRAM read and write will be reset, and the data amount information in the first 15 seconds will be saved, ensuring that each 15 seconds of reading and writing starts from the zero address, and it is also convenient to read the data. After the handover is successful, a data ready signal is given indicating that the host can read the data. The PC104 interface module is responsible for communication and data transmission between the acquisition card and the host computer.

Complete the read and write switching of two SRAMs. At the same time of switching, the address of the SRAM read and write will be reset, and the data amount information of just 15 will be saved, ensuring that each 15 seconds of reading and writing starts from the zero address, and it is also convenient to read the data. After the handover is successful, a data ready signal is given indicating that the host can read the data. The PC104 interface module is responsible for communication and data transmission between the acquisition card and the host computer.

figure 2

3 DSP hardware and software design

3.1 DSP hardware design

The DSP uses McBSP to communicate with the audio CODEC. The system block diagram (two-channel audio receiving block diagram) is shown in Figure 3. The McBSP relies on three signals to receive data: the data line DR, the frame sync line FSR, and the shift clock line CLKR. The DR pin finishes receiving audio data from the audio CODEC, and the clock and frame synchronization are controlled by CLKR and FSR. When receiving data, the data from the DR pin reads data from the data register DRR under the action of FSR and CLKR. CLKR, FSR can be generated either by an internal sample rate generator or by an external device. In this audio system, the CLKR and FSR signals are all from the FPGA.

In order to reduce the CPU load, the audio data is transmitted using the DMA mechanism. The TMS320VC5416 has six independently programmable DMA channels, each of which is controlled by its own five 16-bit registers: source address register DMSRC, destination address register DMDST, unit count register DMCTR, synchronization event and frame count register DMSFC, transmit mode Control register DMMCR.

By setting the DMA1 channel combined with the McBSP1 channel to read the converted data of the PCM3008 as an example: select the receiving register DRR11 (41h) of the McBSP1 channel as the first address of the DMA transfer data, and select the source address to work after the access is not adjusted, select The DMA channel synchronization event McBSP1 receives the event as a DMA synchronization event to implement the combination of DMA and McBSP. The converted data of PCM3008 is sent to the TMS320VC5416 internal receiving register DRR11 according to the setting of McBSP1, and then the DMA reads the number in DRR11 to the specified data storage area to complete the data acquisition. The DMA does not affect the normal operation of the CPU when transmitting external data. When the DMA collects a specified number of data, a DMA interrupt event is generated to interrupt the CPU to notify the CPU to perform corresponding processing. At this time, the DMA can Continue to collect the next set of data according to the settings, and realize parallel operation of data acquisition and CPU processing.

image 3

3.2 Software Design Process

The program flow is shown in Figure 4. After the system is powered on, first initialize the CPU, McBSP, DMA registers, and then open the interrupt. When all DMA transfers are completed, a status flag is given to inform the CPU that the audio data is ready and the CPU will be original. The audio data is concentrated in a buffer and begins to call the audio processing algorithm to process each audio data in turn, and the processed audio data is sent out through the bus. Then continue to wait for the next frame of audio data, and then repeat.

Figure 4

3.3 Audio compression algorithm

Since the signal frequency required by the system audio is in the range of 150hz-6000hz, a broadband audio algorithm must be used, and we have designed a wideband speech coding. The code rate is variable from 24 kbps to 64 Kbps. The main parameters are as shown in Table 1: Table 1 Main parameters of audio coding

5 Conclusion

The multi-channel audio capture card designed in this paper can realize the acquisition and processing of 8 channels of microphone signals and 2 channels of VHF (very high frequency) signals. The amount of data generated in 24 hours is less than 1.6 GB, and the sound quality meets the requirements of audio requirements in IEC 61996-2. The multi-channel audio capture card has been successfully applied to the shipborne navigation data recorder and passed the Chinese class. The CCS inspection, the VDR system equipped with the multi-channel audio capture card has been put into practical use.

The author of this paper is innovative: it adopts autonomous audio coding algorithm design and realizes it with DSP chip. It uses clever ping-pong design in data storage and reading.

references:

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[2] An Ying, Liu Lina; Design of high-speed signal acquisition and processing system based on DSP, microcomputer information, 2005, 01.

[3] Yu Fangping; Research and Design of Shipborne Voyage Data Recorder (VDR), China Navigation, 2002, 02.

[4] Chang Yong, Qiu Xiaozhu; Serial bus interface design of shipborne navigation data recorder system, China Water Transport, 2004.4.