PLL and DLL: are phase-locked loops, what is the difference?

Generally, there are many PLLs on Altera's products, and xilinux's products are more DLLs. I thought it was a different statement from the two companies. Later, I saw someone asking the difference between the two on the forum. Look closely, it turns out to be two different guys. The DLL is based on a digital sampling method that inserts a delay between the input clock and the feedback clock to align the input clock with the rising edge of the feedback clock. Also known as digital phase locked loop.

The PLL uses a voltage control delay, using the VCO to implement the delay function of the class test in the DLL. Also known as analog phase-locked loop. Function can achieve multiplier, frequency division, duty cycle adjustment, but the PLL adjustment range is larger, for example: XILINX uses DLL, only 2, 4 times the frequency; ALTERA PLL can achieve a larger frequency range After all, one is analog and the other is digital. The contrast between the two: for the PLL, the crystal oscillator used is unstable, and will accumulate phase errors, and the DLL is better at this point, and the anti-noise ability is stronger; but the PLL does the integration of the clock. Better. In general, PLL applications are many, and DLLs are superior to PLLs in terms of jitter power precision.

At present, most FPGA manufacturers integrate a hard DLL (Delay-Locked Loop) or a PLL (Phase-Locked Loop) in the FPGA to complete the high-precision, low-jitter multiplier, frequency division, and duty cycle adjustment of the clock. Move equal. At present, the DLL and PLL resources of high-end FPGA products are becoming more and more abundant, the functions are more and more complex, and the precision is getting higher and higher (generally in the order of ps). The Xilinx chip is mainly integrated with a DLL, while the Altera chip is integrated with a PLL. The module name of the Xilinx chip DLL is CLKDLL. In the high-end FPGA, the enhanced module of CLKDLL is DCM (Digital Clock Manager).

The PLL module of the Altera chip is also divided into an enhanced PLL (Enhanced PLL) and a high speed (Fast PLL). The generation and configuration methods of these clock modules are generally divided into two types, one is directly instantiated in the HDL code and the schematic diagram, and the other method is to configure relevant parameters in the IP core generator to automatically generate IP. Xilinx's IP core generator is called Core Generator, and the DCM module is generated by the Archetecture Wizard in the Xilinx ISE 5.x version. Altera's IP core generator is called MegaWizard. In addition, the constraints of the clock module can be completed by writing constraint attributes in the constraint file of the synthesis and implementation steps.