Try to avoid the use of global reset in FPGA development? (1)

In recent days, I read a very interesting white paper (white paper, wp272.pdf) on the Xilinx website, called "Get Smart About Reset: Think Local, Not Global". I share my thoughts here, including little attention in previous designs. Some details of the arrival.
In digital system design, we have traditionally believed that a master reset should be set for all flip-flops, which will greatly facilitate subsequent testing. Therefore, in all programs, I often use the same reset signal in the port definition (in fact, it is not used at all). So, when you see the documentation mentioning, "It is not recommended to use global reset in FPGA design, or should try to avoid this design approach", many designers (including me) will find it very difficult to understand, this design idea It is in conflict with our usual understanding!
Continue reading, unwittingly discovering that this white paper is really reasonable. Let me talk about my personal understanding.
1. Is global reset a critical timing?
The global reset signal is generally obtained in the following three ways:
1. The first, most common, is to use a reset button to generate a reset signal to the global reset pin of the FPGA. Its speed is obviously very slow (because it is a mechanical structure), and there is a problem of jitter.
2. The second type is generated by the power chip when power is on. For example, TI's TPS76x series power system can generally generate a reset signal for power-on reset of the main chip.
3. The third type is the reset pulse generated by the control chip, which is convenient for our designers to use program control.
In these cases, the change of the reset signal seems to be slow compared to the internal signal of the FGPA chip. For example, the reset button generates a reset signal with a period of at least milliseconds, and the internal signal of our FPGA is often nanometer or Microsecond level. The frequency of the reset signal is so low that our task is not a critical timing (not TIming-criTIcal). Even with timing constraints on such signals, the period of the constraints is very long. The period of the global reset pulse is much larger than the clock period, so it is conventionally assumed that all flip-flops in the FPGA chip can be effectively reset.
However, with the rapid increase in FPGA performance and operating frequency, this assumption is no longer valid. At this point, the generation of the global reset signal becomes a critical issue in timing.