Xilinx Verilog (FPGA/CPLD) design skills

The following is a list of common mistakes made in the design. These errors often make your design unreliable or slow. In order to improve your design performance and improve the reliability of the speed you must determine your design through all of these checks.

Reliability Select the global clock buffer BUFG for the clock signal
A clock that does not use the global clock buffer will introduce a bias.

Using only one clock edge to register data using the two edges of the clock is unreliable because some or both edges of the clock will drift; if the clock drifts and you only use one edge of the clock, you reduce the clock edge drift. risks of.
This problem can be solved by allowing CLKDLL to automatically correct the duty cycle of the clock to a 50% duty cycle. Otherwise it is strongly recommended that you only use one clock edge.

Do not generate a clock internally except for clocks generated with CLKDLL or DCM.
This includes generating a gated clock and a divided clock. Alternatively, a clock enable can be established or a different clock signal can be generated using CLKDLL or DCM.
For a purely synchronous design it is recommended that you use only one clock whenever possible.

Reliability Select the global clock buffer BUFG for the clock signal
A clock that does not use the global clock buffer will introduce a bias.

Using only one clock edge to register data using the two edges of the clock is unreliable because some or both edges of the clock will drift; if the clock drifts and you only use one edge of the clock, you reduce the clock edge drift. risks of.
This problem can be solved by allowing CLKDLL to automatically correct the duty cycle of the clock to a 50% duty cycle. Otherwise it is strongly recommended that you only use one clock edge.

Do not generate a clock internally except for clocks generated with CLKDLL or DCM.
This includes generating a gated clock and a divided clock. Alternatively, a clock enable can be established or a different clock signal can be generated using CLKDLL or DCM.
For a purely synchronous design, it is recommended that you use only one clock whenever possible. Do not generate asynchronous control signals internally, such as reset signals or asynchronous control signals generated internally by the set signal. Glitch can be used instead to generate a synchronous reset. Set signal This signal is decoded one clock cycle ahead of the time when it needs to be active.

Don't use multiple clocks without phase relationships. You may not always be able to avoid this condition. Under these circumstances, make sure you have used the appropriate synchronization circuit to cross the clock domain.

Don't use multiple clocks without phase relationships. Again, you may not always be able to avoid this condition. Many designs need to do this. In these cases, you determine that you have properly constrained the path across the clock domain.

Do not use internal latch internal latches to confuse timing and often introduce additional clock signals. Internal latches can be considered as combinatorial logic when the transparent gate is open but can be considered synchronous when the gate is latched. This will confuse timing analysis. Internal latches often introduce gated clocks. Gated clocks can cause glitches that make the design unreliable.

The logic level delay should not exceed 50% of the timing budget. Each path logic level delay can be found in the logic level timing report or post-layout timing report. After each path is analyzed, the timing analyzer will generate each path. The statistics of the delay check that the total logic level delay exceeds 50% of your timing budget?

IOB register
The IOB register provides the fastest clock-to-output and input-to-clock delay. First, there are some restrictions. For the input register, there can be no combined logic between the pin and the register. For the output register, there can be no combination between the register and the pin. Logic exists for the three-state output. All registers in the IOB must use the same clock signal and reset signal and the IOB tri-state register must be active low to put into the IOB. The tristate buffer is active low so in the register and three There is no need for an inverter between the state buffers. You must enable the software to select the IOB register. You can set the global implementation option to select the IOB register for the input/output or input and output. The default value is off.
You can also set in the synthesis tool or in the user constraint file UCF to enable the use of the IOB register syntax: INST IOB = TRUE;

Choose a fast slew rate for critical outputs. Choose a slew rate for LVCMOS and LVTTL levels. Fast slew rate reduces output delay but increases ground bounce so you must choose a fast slew rate based on careful consideration.

Pipeline Logic If your design allows for increased latency, the pipelined operation of the combinatorial logic can improve performance. There are a large number of registers in the Xilinx FPGA. For each four-input function generator, there is a corresponding register that uses these registers in the case of sacrificial delay. Increase data throughput

Code optimization for a four-input lookup table structure Remember that each lookup table can create a four-input combinatorial logic function. If you need more functionality, remember the number of lookup tables needed to implement the function.

Using a Case statement instead of an if-then-else statement A complex if-then-else statement usually generates a priority decoding logic. This will increase the combined delay on these paths. Case statements used to generate complex logic will usually generate no. Parallel logic with too much latency for Verilog users can use the compile wizard synopsys parallel_case